Why Do I Only Get One Wait-State with the A7 "Wait Control" Module?

Within the FastChip soft module library, there is a Wait Control module that allows you to add wait-states to a CSI bus transaction, beyond the first wait-state caused by the addressed Selector or Chip Select module.

When using FastChip 2.2.0 with the A7 family, however, you will always see just one wait-state, regardless of the number of additional wait-states specified. This is due to a bug in the Wait Control logic for the A7.

Work-Around

To work around this bug, you can create a wait-state control function using a third-party logic design package and import a correct design.

This bug is due to be fixed in the next release of FastChip.

FastChip Version: 2.2.0

This solution may or may not apply to other versions of the FastChip development system.